Computer Hardware

Fiber tracking (FT) and quantification algorithms are approximations of reality due to limited spatial resolution, model assumptions, user-defined parameter settings, and physical imaging artifacts resulting from diffusion sequences. Until now, correctness, plausibility, ...

Modern radio telescopes like the Square Kilometer Array (SKA) will need to process in real-time exabytes of radio-astronomical signals to construct a high-resolution map of the sky. Near-Memory Computing (NMC) could alleviate the performance bottlenecks due to frequent memory accesses in a state-of-the-art radio-astronomy imaging algorithm. In this paper, we show that a sub-module performing a two-dimensional fast Fourier transform (2D FFT) is memory bound using CPI breakdown analysis on IBM Power9. Then, we present an NMC approach on FPGA for 2D FFT that outperforms a CPU by up to a factor of 120x and performs comparably to a high-end GPU, while using less bandwidth and memory.

Future applications need new computer systems with new properties pursued. Our presentation for ICT-2014 even initiated by EC in Florence address this. We are planning to submit this project in April 2015 for ICT call. Those who want to be part of the future - you are welcome!

V. SUMMARY We have given parallel algorithms for recognizing and parsing context-free languages on a hypercube of p PE's, 1 5 p 5 n. The algorithms are both time-wise and space-wise optimal with respect to the most efficient sequential algorithm. The recognition algorithms were ...

In this paper, a methodology for the development of fault-tolerant adders based on the radix 2 signed digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free" property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.

... Sensory information comes from a Laser Range Finder also developed by the author [6]. Range data are made up of hundreds of 2D relative coordinate points of targets in the field of view of the sensor camera, already filtered and grouped ... [2] JC Garcı́a, M. Marrón, JA Garcı́a, J ...

Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FP...