This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also compares the performance improvement of Multi-gate Bulk and SOI MOSFET over Single-gate bulk and SOI MOSFET.The simulation results are obtained with the help of TCAD 3-D device simulator are well matched with the ideal characteristics.

Fin-type Field-Effect Transistors (FinFETs) are the prospective promised solutions in deep submicron CMOS technologies due to the challenges that face MOSFET transistors, especially short-length channel. The short-channel transistor produces two current paths that control the channel barrier height due to the internal capacitances formation. The finFET is a double-gate transistor to improve the off-current and not to have a silicon far from the gate. In this paper, a comparative study on optimized finFET transistors alongside the nanoscale that enhances the short channel challenges is introduced. The finFET design enhancements include a silicon-on-insulator (SOI), shallow trench isolation (STI), Ultra-Thin Body SOI (UTBSOI), multi-gate structure and stacked-channel structure.

This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W F =5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.