https://www.ijert.org/vlang-and-systemverilog-verification-languages-a-comparision https://www.ijert.org/research/vlang-and-systemverilog-verification-languages-a-comparision-IJERTV3IS050827.pdf Verification of the design has become a critical issue due to the increasing complexity of the chip according to the Moore's law. On the other hand in the present scenario the Moore's law no longer persists as no further reduction in the chip size is possible, hence Amdahl's law is the main area of focus. About 70% of the design effort is consumed in the verification, so productivity, reusability and multi-threading in multi-core processors have become the key issues. SystemVerilog and Valng are the languages providing the means of reusability and productivity through the creation of the Verification IP. The edge that VLang has over SystemVerilog is the multi-threading feature which helps in faster simulation and hence more efficient. The VLang uses the D language as its base. The most significant feature is that Vlang is Open Source.